The present invention relates to an amplifier circuit and, more particularly, to an intermediate frequency amplifier circuit having a negative feedback circuit.
An example of a conventional intermediate frequency amplifier is shown in FIG. 1. An intermediate frequency signal is supplied from a signal source 50 through a coupling capacitor 1 to a differential amplifier circuit 11. This circuit 11 is composed of a plurality of differential amplifiers connected in a cascade manner. In this drawing, however, only an initial stage differential amplifier 2 and the last stage differential amplifier 3 are shown. Although each of the differential amplifiers 2-3 has inverting and non-inverting inputs and true and complementary outputs, they are connected such that the differential amplifier circuit 11 has first and second input nodes B and C and first and second output nodes D and E. Moreover, the signal at the first output node D is opposite in phase to the signal at the first input node B and further to the signal at the second output node C. The output node D is connected to an output terminal 10.
The input signal is subject to the d.c. blocking by the capacitor 1. That is, an a.c. component of the input signal is supplied to the first input node D of the differential amplifier circuit 11 and then amplified by each of the amplifiers 2-3 in the differential amplifier circuit 11. The true output signal at the output node D of the differential amplifier circuit 11 is supplied to the output terminal 10 and further fed back to the first input node B through a low-pass filter 13. The complementary output signal at the node E is also fedback to the second input node C through a low-pass filter 12. Thus, two negative feedback look are provided to construct a self-bias circuit.
The low-pass filter 13 is composed of a resistor 7 and a filter capacitor 9, and the output of the low-pass filter 13 is supplied to the input node B through a resistor 5. This resistor 5 determines an input impedance of the differential amplifier circuit 11. The low-pass filter 12 is composed of a resistor 6 and a filter capacitor 8. The low-pass filters 12 and 13 thus constituted function to cut off an a.c. component of the true and complementary output signals of the differential amplifier circuit 11 and to allow a d.c. component thereof to be fed back to thereby stabilize a d.c. operating point of the differential amplifier circuit 11, respectively.
In the intermediate frequency amplifier circuit thus constructed, a loop gain Gb of a loop from the node B through the differential amplifier circuit 11 and the node D to the node F which is an output of the low-pass filter 13 is given by the following equation (1): EQU Gb=G11(1+.omega..sup.2 Cf.sup.2 Rf.sup.2).sup.-(1/2) ( 1)
where G11 is a gain of the differential amplifier circuit 11, Rf is a resistance value of each of the feedback resistors 6 and 7, Cf is a capacitance of each of the filter capacitors 8 and 9 and .omega. is an angular frequency of the signal.
Generally, in a feedback circuit, representing an open loop gain by G (G11 in the above equation (1)), a feedback factor by .beta., G.multidot..beta. is a loop gain and, thus, in FIG. 1, the loop gain Gb in the equation (1) corresponds to a gain of the portion from the node B through the node D to the node F when the feedback path is cut immediately after, for example, the biasing resistor 5.
Further, since the feedback loop including the nodes C, E and G has the same construction as that of the feedback loop including the nodes B, D and F, a loop gain Gc of the portion from the node C through the differential amplifier circuit 11 and the node E to the node G which is the output of the low-pass filter 12 is equal to Gb. Therefore, the following equation (2) is established: EQU Gc=Gb (2)
That is, the signals which are the same in magnitude and opposite in phase are fedback to the nodes B and C connected to the inputs of the differential amplifier circuit 11, respectively.
Therefore, a feedback gain Gr (loop gain of the differential signal) of the differential output between the nodes F and G with respect to the differential input between the nodes B and C can be represented from the equations (1) and (2) by the following equation (3): ##EQU1##
In such conventional intermediate frequency amplifier circuit, the feedback gain is determined by the capacitance Cf and the resistance Rf of the capacitors and the resistors constituting the low-pass filters 12 and 13 as shown by the equation (3). However, when, in order to miniaturize circuit elements, the capacitance Cf and feedback resistance Rf are made smaller, the feedback gain Gf becomes large, leading to degradation of oscillation stability.
In order to stabilize the operation of such intermediate frequency amplifier circuit, Japanese Patent Application Laid-open No. Hei 3-255711 proposes an intermediate frequency amplifier circuit which comprises d.c. voltage feedback means for applying a predetermined feedback voltage to an output of a predetermined one of transistors included in a last stage differential amplifier thereof and feeding back it to a predetermined one of transistors included in an initial differential amplifier and biasing means for applying a biasing voltage which is substantially equal to the feedback voltage supplied by the d.c. voltage feedback means to another transistor of the initial state differential amplifier than the predetermined transistor thereof.
In the proposed intermediate frequency amplifier circuit mentioned above, the operation thereof is stabilized by performing the d.c. feedback such that the feedback voltage from the last stage differential amplifier which is related to the d.c. feedback becomes equal to the biasing voltage of the transistor of the initial stage differential amplifier.
In the proposed intermediate frequency amplifier circuit, however, a biasing circuit for making the feedback voltage from the last stage differential amplifier equal to the biasing voltage of the transistor of the initial stage differential amplifier is required. Therefore, the number of circuit elements is not reduced and rather the circuit size becomes larger.
Further, in the proposed amplifier circuit, in order to set the feedback gain, it is necessary to determine the bias by means of the d.c. feedback means and the feedback voltage and, thus, in order to reduce the circuit element size, the biasing circuit itself must be miniaturized. Further, in order to obtain a required biasing voltage, there is a limit in reducing the element size, necessarily.